From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arne Fitzenreiter To: development@lists.ipfire.org Subject: [PATCH] u-boot: add nanopi r2c support Date: Sun, 23 Apr 2023 08:04:22 +0000 Message-ID: <20230423080422.441678-1-arne_f@ipfire.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="===============6699306805504901772==" List-Id: --===============6699306805504901772== Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable this patch add nanopi r2c plus support. if this u-boot is installed on the eMMC this is also supported. Signed-off-by: Arne Fitzenreiter --- config/rootfiles/common/aarch64/u-boot | 2 + lfs/u-boot | 20 +++ .../u-boot/rockchip/add_nanopi-r2c.patch | 169 ++++++++++++++++++ .../u-boot/rockchip/generate-2-ethaddr.diff | 18 -- 4 files changed, 191 insertions(+), 18 deletions(-) create mode 100644 src/patches/u-boot/rockchip/add_nanopi-r2c.patch delete mode 100644 src/patches/u-boot/rockchip/generate-2-ethaddr.diff diff --git a/config/rootfiles/common/aarch64/u-boot b/config/rootfiles/common= /aarch64/u-boot index 2b60c7802..4b2dcd4fd 100644 --- a/config/rootfiles/common/aarch64/u-boot +++ b/config/rootfiles/common/aarch64/u-boot @@ -6,6 +6,8 @@ boot/u-boot-rpi4.bin boot/uEnv.txt boot/uboot.env #usr/share/u-boot +#usr/share/u-boot/nanopi_r2c +usr/share/u-boot/nanopi_r2c/u-boot-rockchip.bin #usr/share/u-boot/nanopi_r2s usr/share/u-boot/nanopi_r2s/u-boot-rockchip.bin #usr/share/u-boot/nanopi_r4s diff --git a/lfs/u-boot b/lfs/u-boot index 0d4c2cc58..cea74e64c 100644 --- a/lfs/u-boot +++ b/lfs/u-boot @@ -137,6 +137,26 @@ ifneq "$(MKIMAGE)" "1" /usr/share/u-boot/nanopi_r2s/u-boot-rockchip.bin cd $(DIR_APP) && make distclean =20 + # Nanopi R2C + cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/u-boot/rockchip/add_na= nopi-r2c.patch + cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER) + cd $(DIR_APP) && tar axf $(DIR_DL)/arm-trusted-firmware-$(ATF_VER).tar.gz + cd $(DIR_APP)/arm-trusted-firmware-$(ATF_VER) && make PLAT=3Drk3328 ARCH=3D= aarch64 DEBUG=3D0 bl31 LDFLAGS=3D"$(LDFLAGS)" + cd $(DIR_APP) && cp arm-trusted-firmware-$(ATF_VER)/build/rk3328/release/bl= 31/bl31.elf bl31.elf + cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER) + -mkdir -pv /usr/share/u-boot/nanopi_r2c + + cd $(DIR_APP) && make CROSS_COMPILE=3D"" nanopi-r2c-rk3328_config + cd $(DIR_APP) && sed -i -e 's!^CONFIG_IDENT_STRING=3D.*!CONFIG_IDENT_STRING= =3D" Nanopi R2C - IPFire.org"!' .config + cd $(DIR_APP) && sed -i -e 's!^CONFIG_BOOTCOMMAND=3D.*!CONFIG_BOOTCOMMAND= =3D"console=3DttyS2,115200n8;run distro_bootcmd"!' .config + cd $(DIR_APP) && sed -i -e 's!^CONFIG_BAUDRATE=3D.*!CONFIG_BAUDRATE=3D11520= 0!' .config + cd $(DIR_APP) && sed -i -e 's!.*CONFIG_ENV_OVERWRITE.*!CONFIG_ENV_OVERWRITE= =3Dy!' .config + cd $(DIR_APP) && make CROSS_COMPILE=3D"" HOSTCC=3D"gcc $(CFLAGS)" + cd $(DIR_APP) && install -v -m 644 u-boot-rockchip.bin \ + /usr/share/u-boot/nanopi_r2c/u-boot-rockchip.bin + cd $(DIR_APP) && make distclean + + # Nanopi R4S # arm trusted firmware for rk3399 cannot build without cortex m0 gcc crossc= ompiler # it is build on ubuntu with make PLAT=3Drk3399 ARCH=3Daarch64 DEBUG=3D0 bl= 31 diff --git a/src/patches/u-boot/rockchip/add_nanopi-r2c.patch b/src/patches/u= -boot/rockchip/add_nanopi-r2c.patch new file mode 100644 index 000000000..9e330041f --- /dev/null +++ b/src/patches/u-boot/rockchip/add_nanopi-r2c.patch @@ -0,0 +1,169 @@ +diff -Naur u-boot-2022.10.org/arch/arm/dts/Makefile u-boot-2022.10/arch/arm/= dts/Makefile +--- u-boot-2022.10.org/arch/arm/dts/Makefile 2022-10-03 19:25:32.000000000 += 0000 ++++ u-boot-2022.10/arch/arm/dts/Makefile 2023-04-22 15:02:25.945603949 +0000 +@@ -124,6 +124,7 @@ +=20 + dtb-$(CONFIG_ROCKCHIP_RK3328) +=3D \ + rk3328-evb.dtb \ ++ rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2s.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ +diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi u-b= oot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi +--- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi 1970-01-01= 00:00:00.000000000 +0000 ++++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi 2023-04-22 15:= 07:54.544953841 +0000 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++#include "rk3328-nanopi-r2s-u-boot.dtsi" +diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts u-boot-2022= .10/arch/arm/dts/rk3328-nanopi-r2c.dts +--- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts 1970-01-01 00:00:0= 0.000000000 +0000 ++++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c.dts 2023-04-22 15:07:07.86= 1614679 +0000 +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++/dts-v1/; ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model =3D "FriendlyElec NanoPi R2C"; ++ compatible =3D "friendlyarm,nanopi-r2c", "rockchip,rk3328"; ++}; ++ ++&emmc { ++ bus-width =3D <8>; ++ cap-mmc-highspeed; ++ max-frequency =3D <150000000>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names =3D "default"; ++ pinctrl-0 =3D <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply =3D <&vcc_io_33>; ++ vqmmc-supply =3D <&vcc18_emmc>; ++ status =3D "okay"; ++}; +diff -Naur u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig u-boot-202= 2.10/configs/nanopi-r2c-rk3328_defconfig +--- u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig 1970-01-01 00:00:= 00.000000000 +0000 ++++ u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig 2023-04-22 15:09:20.8= 43584447 +0000 +@@ -0,0 +1,112 @@ ++CONFIG_ARM=3Dy ++CONFIG_SKIP_LOWLEVEL_INIT=3Dy ++CONFIG_COUNTER_FREQUENCY=3D24000000 ++CONFIG_ARCH_ROCKCHIP=3Dy ++CONFIG_SYS_TEXT_BASE=3D0x00200000 ++CONFIG_SPL_GPIO=3Dy ++CONFIG_NR_DRAM_BANKS=3D1 ++CONFIG_ENV_OFFSET=3D0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE=3D"rk3328-nanopi-r2c" ++CONFIG_ROCKCHIP_RK3328=3Dy ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=3Dy ++CONFIG_TPL_LIBCOMMON_SUPPORT=3Dy ++CONFIG_TPL_LIBGENERIC_SUPPORT=3Dy ++CONFIG_SPL_DRIVERS_MISC=3Dy ++CONFIG_SPL_STACK_R_ADDR=3D0x600000 ++CONFIG_DEBUG_UART_BASE=3D0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=3D24000000 ++CONFIG_SYS_LOAD_ADDR=3D0x800800 ++CONFIG_DEBUG_UART=3Dy ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=3Dy ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=3D0x300000 ++CONFIG_TPL_SYS_MALLOC_F_LEN=3D0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=3Dy ++CONFIG_FIT_VERBOSE=3Dy ++CONFIG_SPL_LOAD_FIT=3Dy ++CONFIG_DEFAULT_FDT_FILE=3D"rockchip/rk3328-nanopi-r2c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=3Dy ++CONFIG_MISC_INIT_R=3Dy ++CONFIG_SPL_MAX_SIZE=3D0x40000 ++CONFIG_SPL_PAD_TO=3D0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=3Dy ++CONFIG_SPL_BSS_START_ADDR=3D0x2000000 ++CONFIG_SPL_BSS_MAX_SIZE=3D0x2000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK=3D0x400000 ++CONFIG_SPL_STACK_R=3Dy ++CONFIG_SPL_I2C=3Dy ++CONFIG_SPL_POWER=3Dy ++CONFIG_SPL_ATF=3Dy ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=3Dy ++CONFIG_TPL_SYS_MALLOC_SIMPLE=3Dy ++CONFIG_CMD_BOOTZ=3Dy ++CONFIG_CMD_GPT=3Dy ++CONFIG_CMD_MMC=3Dy ++CONFIG_CMD_USB=3Dy ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=3Dy ++CONFIG_SPL_OF_CONTROL=3Dy ++CONFIG_TPL_OF_CONTROL=3Dy ++CONFIG_OF_SPL_REMOVE_PROPS=3D"clock-names interrupt-parent assigned-clocks = assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=3Dy ++CONFIG_ENV_IS_IN_MMC=3Dy ++CONFIG_SYS_RELOC_GD_ENV_ADDR=3Dy ++CONFIG_SYS_MMC_ENV_DEV=3D1 ++CONFIG_NET_RANDOM_ETHADDR=3Dy ++CONFIG_TPL_DM=3Dy ++CONFIG_REGMAP=3Dy ++CONFIG_SPL_REGMAP=3Dy ++CONFIG_TPL_REGMAP=3Dy ++CONFIG_SYSCON=3Dy ++CONFIG_SPL_SYSCON=3Dy ++CONFIG_TPL_SYSCON=3Dy ++CONFIG_CLK=3Dy ++CONFIG_SPL_CLK=3Dy ++CONFIG_FASTBOOT_BUF_ADDR=3D0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=3Dy ++CONFIG_ROCKCHIP_GPIO=3Dy ++CONFIG_SYS_I2C_ROCKCHIP=3Dy ++CONFIG_MMC_DW=3Dy ++CONFIG_MMC_DW_ROCKCHIP=3Dy ++CONFIG_SF_DEFAULT_SPEED=3D20000000 ++CONFIG_ETH_DESIGNWARE=3Dy ++CONFIG_GMAC_ROCKCHIP=3Dy ++CONFIG_PINCTRL=3Dy ++CONFIG_SPL_PINCTRL=3Dy ++CONFIG_DM_PMIC=3Dy ++CONFIG_PMIC_RK8XX=3Dy ++CONFIG_SPL_PMIC_RK8XX=3Dy ++CONFIG_SPL_DM_REGULATOR=3Dy ++CONFIG_REGULATOR_PWM=3Dy ++CONFIG_DM_REGULATOR_FIXED=3Dy ++CONFIG_SPL_DM_REGULATOR_FIXED=3Dy ++CONFIG_REGULATOR_RK8XX=3Dy ++CONFIG_PWM_ROCKCHIP=3Dy ++CONFIG_RAM=3Dy ++CONFIG_SPL_RAM=3Dy ++CONFIG_TPL_RAM=3Dy ++CONFIG_DM_RESET=3Dy ++CONFIG_BAUDRATE=3D1500000 ++CONFIG_DEBUG_UART_SHIFT=3D2 ++CONFIG_SYSINFO=3Dy ++CONFIG_SYSRESET=3Dy ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=3Dy ++CONFIG_USB_XHCI_HCD=3Dy ++CONFIG_USB_XHCI_DWC3=3Dy ++CONFIG_USB_EHCI_HCD=3Dy ++CONFIG_USB_EHCI_GENERIC=3Dy ++CONFIG_USB_OHCI_HCD=3Dy ++CONFIG_USB_OHCI_GENERIC=3Dy ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=3D1 ++CONFIG_USB_DWC2=3Dy ++CONFIG_USB_DWC3=3Dy ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=3Dy ++CONFIG_USB_GADGET_DWC2_OTG=3Dy ++CONFIG_SPL_TINY_MEMSET=3Dy ++CONFIG_TPL_TINY_MEMSET=3Dy ++CONFIG_ERRNO_STR=3Dy diff --git a/src/patches/u-boot/rockchip/generate-2-ethaddr.diff b/src/patche= s/u-boot/rockchip/generate-2-ethaddr.diff deleted file mode 100644 index 067c8b503..000000000 --- a/src/patches/u-boot/rockchip/generate-2-ethaddr.diff +++ /dev/null @@ -1,18 +0,0 @@ -diff -Naur u-boot-2021.07.org/arch/arm/mach-rockchip/misc.c u-boot-2021.07/a= rch/arm/mach-rockchip/misc.c ---- u-boot-2021.07.org/arch/arm/mach-rockchip/misc.c 2021-07-05 15:11:28.000= 000000 +0000 -+++ u-boot-2021.07/arch/arm/mach-rockchip/misc.c 2021-10-08 10:47:13.7048063= 67 +0000 -@@ -49,9 +49,12 @@ - memcpy(mac_addr, hash, 6); -=20 - /* Make this a valid MAC address and set it */ -- mac_addr[0] &=3D 0xfe; /* clear multicast bit */ -- mac_addr[0] |=3D 0x02; /* set local assignment bit (IEEE802) */ -+ mac_addr[0] =3D 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); -+ if (env_get("eth1addr")) -+ return 0; -+ mac_addr[0] =3D 0x12; /* set local assignment bit (IEEE802) */ -+ eth_env_set_enetaddr("eth1addr", mac_addr); - #endif - return 0; - } --=20 2.34.1 --===============6699306805504901772==--