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- Log ----------------------------------------------------------------- commit 62667a709f9ed5e996e43ebb38bd11ff9e6b559f Author: Michael Tremer michael.tremer@ipfire.org Date: Tue Feb 11 16:54:48 2014 +0100

linux: Fix grsecurity-related crash on Intel Haswell CPUs.

commit a25a2c3190cb841af64d10f1e7197011c0aac969 Author: Michael Tremer michael.tremer@ipfire.org Date: Tue Feb 11 16:54:09 2014 +0100

tor: Update to 0.2.4.20.

-----------------------------------------------------------------------

Summary of changes: lfs/linux | 1 + lfs/tor | 4 +- src/patches/grsecurity-haswell-32bit-fix.patch | 53 ++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 2 deletions(-) create mode 100644 src/patches/grsecurity-haswell-32bit-fix.patch

Difference in files: diff --git a/lfs/linux b/lfs/linux index a422d7a..08fa9a3 100644 --- a/lfs/linux +++ b/lfs/linux @@ -124,6 +124,7 @@ $(TARGET) : $(patsubst %,$(DIR_DL)/%,$(objects)) ifneq "$(KCFG)" "-headers" cd $(DIR_APP) && xz -c -d $(DIR_DL)/$(GRS_PATCHES) | patch -Np1 cd $(DIR_APP) && rm localversion-grsec + cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/grsecurity-haswell-32bit-fix.patch cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.7-disable-compat_vdso.patch endif

diff --git a/lfs/tor b/lfs/tor index 10eaca4..9669ea7 100644 --- a/lfs/tor +++ b/lfs/tor @@ -24,7 +24,7 @@

include Config

-VER = 0.2.4.18-rc +VER = 0.2.4.20

THISAPP = tor-$(VER) DL_FILE = $(THISAPP).tar.gz @@ -44,7 +44,7 @@ objects = $(DL_FILE)

$(DL_FILE) = $(DL_FROM)/$(DL_FILE)

-$(DL_FILE)_MD5 = 6cc5bc776e9d61a9fb1b000609ed2692 +$(DL_FILE)_MD5 = a8cd8e3b3a3f6a7770f2c22d280f19b8

install : $(TARGET)

diff --git a/src/patches/grsecurity-haswell-32bit-fix.patch b/src/patches/grsecurity-haswell-32bit-fix.patch new file mode 100644 index 0000000..abff2b0 --- /dev/null +++ b/src/patches/grsecurity-haswell-32bit-fix.patch @@ -0,0 +1,53 @@ +diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h +index 7430027..2124e35 100644 +--- a/arch/x86/include/asm/mmu_context.h ++++ b/arch/x86/include/asm/mmu_context.h +@@ -80,7 +80,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + #if defined(CONFIG_X86_64) && defined(CONFIG_PAX_MEMORY_UDEREF) + if (static_cpu_has(X86_FEATURE_PCID)) { + if (static_cpu_has(X86_FEATURE_INVPCID)) { +- unsigned long descriptor[2]; ++ u64 descriptor[2]; + descriptor[0] = PCID_USER; + asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_SINGLE_CONTEXT) : "memory"); + } else { +@@ -144,7 +144,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + #if defined(CONFIG_X86_64) && defined(CONFIG_PAX_MEMORY_UDEREF) + if (static_cpu_has(X86_FEATURE_PCID)) { + if (static_cpu_has(X86_FEATURE_INVPCID)) { +- unsigned long descriptor[2]; ++ u64 descriptor[2]; + descriptor[0] = PCID_USER; + asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_SINGLE_CONTEXT) : "memory"); + } else { +diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h +index 45844c0..ada2172 100644 +--- a/arch/x86/include/asm/tlbflush.h ++++ b/arch/x86/include/asm/tlbflush.h +@@ -18,7 +18,7 @@ + static inline void __native_flush_tlb(void) + { + if (static_cpu_has(X86_FEATURE_INVPCID)) { +- unsigned long descriptor[2]; ++ u64 descriptor[2]; + + descriptor[0] = PCID_KERNEL; + asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_ALL_MONGLOBAL) : "memory"); +@@ -42,7 +42,7 @@ static inline void __native_flush_tlb(void) + static inline void __native_flush_tlb_global_irq_disabled(void) + { + if (static_cpu_has(X86_FEATURE_INVPCID)) { +- unsigned long descriptor[2]; ++ u64 descriptor[2]; + + descriptor[0] = PCID_KERNEL; + asm volatile(__ASM_INVPCID : : "d"(&descriptor), "a"(INVPCID_ALL_GLOBAL) : "memory"); +@@ -77,7 +77,7 @@ static inline void __native_flush_tlb_single(unsigned long addr) + { + + if (static_cpu_has(X86_FEATURE_INVPCID)) { +- unsigned long descriptor[2]; ++ u64 descriptor[2]; + + descriptor[0] = PCID_KERNEL; + descriptor[1] = addr;

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