[git.ipfire.org] IPFire 2.x development tree branch, next, updated. 0e2f9b011b8945dbfdfd3cac9fe1a486c48732e1

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- Log -----------------------------------------------------------------
commit 0e2f9b011b8945dbfdfd3cac9fe1a486c48732e1
Author: Arne Fitzenreiter <arne_f(a)ipfire.org>
Date:   Tue Apr 28 20:51:03 2015 +0200

    openssl: disable ssse3 on amd cpu's
    
    amd with ssse3 (bulldozer and fusion) has serious performance problems
    with the vpaes code. (-evp is 40% slower)

-----------------------------------------------------------------------

Summary of changes:
 lfs/openssl                                            |  3 ++-
 src/patches/openssl-1.0.2a_disable_ssse3_for_amd.patch | 11 +++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 src/patches/openssl-1.0.2a_disable_ssse3_for_amd.patch

Difference in files:
diff --git a/lfs/openssl b/lfs/openssl
index d8925d7..455dcf1 100644
--- a/lfs/openssl
+++ b/lfs/openssl
@@ -117,9 +117,10 @@ $(TARGET) : $(patsubst %,$(DIR_DL)/%,$(objects))
 	cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/openssl-1.0.1m-weak-ciphers.patch
 	cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/openssl-disable-sslv2-sslv3.patch
 
-	# Enable Padlock in i586
+	# i586 specific patches
 ifeq "$(MACHINE)" "i586"
 	cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/openssl-1.0.2a_auto_enable_padlock.patch
+	cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/openssl-1.0.2a_disable_ssse3_for_amd.patch
 endif
 
 	# Apply our CFLAGS
diff --git a/src/patches/openssl-1.0.2a_disable_ssse3_for_amd.patch b/src/patches/openssl-1.0.2a_disable_ssse3_for_amd.patch
new file mode 100644
index 0000000..097cc80
--- /dev/null
+++ b/src/patches/openssl-1.0.2a_disable_ssse3_for_amd.patch
@@ -0,0 +1,11 @@
+diff -Naur openssl-1.0.2a.org/crypto/x86cpuid.pl openssl-1.0.2a/crypto/x86cpuid.pl
+--- openssl-1.0.2a.org/crypto/x86cpuid.pl	2015-03-19 14:30:36.000000000 +0100
++++ openssl-1.0.2a/crypto/x86cpuid.pl	2015-04-28 13:47:57.853521020 +0200
+@@ -71,6 +71,7 @@
+ 	&mov	("eax",1);
+ 	&xor	("ecx","ecx");
+ 	&cpuid	();
++	&and	("ecx",0xfffffdff);	# clear SSSE3 because it is incredible slow on AMD's
+ 	&bt	("edx",28);
+ 	&jnc	(&label("generic"));
+ 	&shr	("ebx",16);


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